The development of a new integrated circuit (IC) device requires not only that the circuit be designed in detail but also that the design be verified through testing. In addition, once a prototype device is available, before it can be released to production, extensive, detailed additional production testing is typically required. Given the extremely large number of transistors in present day IC devices, the development of test programs for both design verification and production has become a complex, time consuming, tedious and expensive process.
Consider that this process typically proceeds by a test engineer first preparing a formal detailed specification for testing the device. This test specification determines a set of logic signals to be applied to each input pin of the device for each of a long sequence of test cycles. Efficient coordination of the test development process is even more complicated if it is being performed during design verification, at which time test patterns may need to be changed and manipulated quickly.
In the case of memory components, the test specification typically defines a set of address, data, and command input signals to be applied to a memory device under test. The development of such specifications was rather straightforward for devices such as dynamic random access memories (DRAMs). However, with the advent of synchronous dynamic random access memories (SDRAMs), testing is more complex because of certain key differences in their internal structure. The most critical such difference for testing is that the operation of an SDRAM is synchronous, such that in order to ensure proper operation, all operations must occur synchronously with a master clock signal. Therefore, the exact timing of events is more critical when developing a test for an SDRAM.
SDRAM arrays can also be split into two or more independent memory banks, and therefore two or more rows of the memory can be active simultaneously. Also, a so-called burst mode allows multiple SDRAM locations to be accessed in sequence. Therefore, in order to fully test an SDRAM device, it becomes necessary to support testing of these different access modes and other operations.
It has been common for some time for a testing to be performed using automatic test equipment (ATE). With such equipment, the test engineer, or a programmer working closely with the test engineer, develops a set of computer instructions for the test in accordance with the test specification. The computer instructions specify the test as a set of program instructions for the test equipment that may be written in a computer language, such as C, Pascal, or a special purpose test equipment language. This test software typically defines the set of test signals mathematically, as a set of "vectors" to be applied to the memory device under test. The values of the vectors determine the state of each of the logic input pins of the device at any given point in time.
A significant drawback to this approach is that a high level of both electronic circuit design and software programming expertise is typically required to create the test software. The process requires a test engineer who understands the nuances of programming and a programmer who understands integrated circuit technology. The situation is now such that it typically requires months of training for either a test engineer or a programmer to become proficient at developing test equipment programs.
In addition, the access cycle time of memory ICs decreases as integrated circuit technologies inevitably improve. The associated test equipment must therefore maintain the same pace and increase its operating speed accordingly. One common approach to solving this problem is to use test equipment that includes multiple pattern generators operating in parallel. However, the presence of parallel hardware pattern generators further complicates the development of test programs, since synchronization of the operations of the various parallel processors must be taken into account.
It has in some instances been possible to take advantage of the developments in computer graphics to help with developing test procedures for logic circuit designs. For example, U.S. Pat. No. 5,371,851 issued to Pieper et al. and assigned to Credence Systems Corporation, describes a system for graphical editing of logic signals using a mouse and cursor. This type of system requires the user to specify a state for each logic signal in each cycle of the test.
In U.S. Pat. No. 5,557,559 issued to Rhodes and assigned to Motay Electronics, Inc., there is similarly described a waveform generator that provides a graphical display of logic signals to be applied to an integrated circuit under test.
However, direct application of these techniques does not particularly provide advantages in the memory testing environment, and particularly for more complicated memory devices such as SDRAM devices that presently require complex programming logic for efficient generation of a complete set of test sequences.